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PDP-11 Architecture

Introduction

TThe PDP-11 architecture was a CISC instruction set architecture developed by Digital Equipment Corporation. It was implemented by central processing units (CPUs) and microprocessors used in PDP-11 minicomputers. It was in wide use during the 1970s, but was overshadowed by the more powerful VAX-11 architecture in the 1980s.

Orthogonal Instruction Set

The PDP-11 processor architecture has a mostly orthogonal instruction set. For example, instead of instructions such as load and store, the PDP-11 has a move instruction for which either operand (source and destination) can be memory or register. There are no specific input or output instructions; the PDP-11 uses memory-mapped I/O and so the same move instruction is used. Orthogonality even enables moving data directly from an input device to an output device. More complex instructions such as add likewise can have memory, register, input or output as source or destination. Most operands can apply any of eight addressing modes to eight registers. The addressing modes provide register, immediate, absolute, relative, deferred (indirect), and indexed addressing, and can specify auto-increment and auto-decrement of a register by one (byte instructions) or two (word instructions). Use of relative addressing lets a machine-language program be position-independent.

Data is stored as sixteen-bit words in little-Endian (with least significant bytes first) format. Thirty two bit data is supported as extensions to the basic architecture, for example floating point in the FPU Instruction Set (FIS), double-words in the Extended Instruction Set (EIS) or long data in the Commercial Instruction Set (CIS) are stored in more than one format.

The CPU contained eight general-purpose 16-bit registers (R0 through R7). Register R7 is the program counter (PC). Although any register can be used as a stack pointer, R6 is the stack pointer (SP) used for hardware interrupts and traps. R5 was often used to point to the current procedure call frame. To speed up context switching, some PDP-11 models provided dual R1-R5 register sets. Kernel, Supervisor (where present), and User modes have separate memory maps, and also separate stack pointers (so that a user program cannot cause the system to malfunction by storing an invalid value in the stack pointer register).

The same instruction set, with small exceptions, were implemented across the entire PDP-11 line. The PDP-11/20 was one of the only PDP-11 computers which had the instruction set implemented as hard-wired logic. All subsequent PDP-11 processors featured micro-coded instruction sets in PROM. This allowed the same instruction set to be implemented across a variety of low and high performing systems. A similar strategy was used by the IBM 360 line in which a customer could purchase a low-end or high-end 360 model and be ensured that developed software ran on all models.

I/O Instructions

Early models of the PDP-11 had no dedicated bus for input/output, but only one bus where processor, memory and I/O devices were added; it was appropriately called the Unibus (Unified Bus). Input and output devices were mapped to memory addresses in a reserved memory space for the I/O devices. An input/output device determined the memory addresses to which it would respond, and specified its own interrupt vector and interrupt priority. This flexible framework provided by the processor architecture made it unusually easy to invent new bus devices, including devices to control hardware that had not been contemplated when the processor was originally designed. DEC openly published the Unibus specifications, even offering prototyping bus interface circuit boards, bus extenders and encouraging customers to develop their own Unibus-compatible hardware.

Higher-performance members of the PDP-11 family, starting with the PDP-11/45 Unibus and 11/83 Q-Bus systems, departed from the single-bus approach. Instead, memory was interfaced by dedicated circuitry and space in the CPU cabinet, while the Unibus continued to be used for I/O only. In the PDP-11/70, this was taken a step further, with the addition of a dedicated interface between disks and tapes and memory, via the MASSBUS. Although input/output devices continued to be mapped into memory addresses, some additional programming was necessary to set up the added bus interfaces. Including a private path from processor to the memory made sense to reduce contention between devices and processor for access to memory. As CPU speeds increased, improvements were required to reduce memory contention. Cache memory options alleviated CPU to memory contention as well.

Interrupts

The PDP-11 supported hardware interrupts at four priority levels. Interrupts were serviced by software service routines, which could specify whether they themselves could be interrupted (achieving interrupt nesting). The event that causes the interrupt is indicated by the device itself, as it informs the processor of the address of its own interrupt vector. Interrupt vectors are blocks of two 16-bit words in low kernel address space (which normally corresponded to low physical memory) between 0 and 776. The first word of the interrupt vector contains the address of the interrupt service routine and the second word the value to be loaded into the PSW (priority level) on entry to the service routine.

To request an interrupt, a bus device would assert one of four common bus lines, BR4 through BR7, until the processor responded. Higher numbers indicated greater urgency, perhaps that data might be lost or a desired sector might rotate out of contact with the read/write heads unless the processor responded quickly. The printer's readiness for another character was the lowest priority (BR4), as it would remain ready indefinitely. If the processor were operating at level 5, then BR6 and BR7 would be in order. If the processor were operating at 3 or lower, it would grant any interrupt; if at 7, it would grant none. Bus requests that were not granted were not lost but merely deferred. The device needing service would continue to assert its bus request.

Whenever an interrupt exceeded the processor's priority level, the processor asserted the corresponding bus grant, BG4 through BG7. The bus-grant lines were not common lines but were a daisy chain. The input of each gate was the output of the previous gate in the chain. A gate was on each bus device, and a device physically closer to the processor was earlier in the daisy chain. If the device had made a request, then on sensing its bus-grant input, it could conclude it was in control of the bus, and did not pass the grant signal to the next device on the bus. If the device had not made a request, it propagated its bus-grant input to its bus-grant output, giving the next closest device the chance to reply. (If devices did not occupy adjacent slots to the processor board, grant continuity cards inserted into the empty slots propagated the bus-grant line.)

Once in control of the bus, the device dropped its bus request and placed on the bus the memory address of its two-word vector. The processor saved the program counter (PC) and Program Status Word (PSW at address 177776), entered Kernel mode, and loaded new values from the specified vector. For a device at BR6, the new PSW in its vector would typically specify 6 as the new processor priority, so the processor would honor more urgent requests (BR7) during the service routine, but defer requests of the same or lower priority. With the new PC, the processor jumped to the service routine for the interrupting device. That routine operated the device, at least removing the condition that caused the interrupt. The routine ended with the RTI (ReTurn from Interrupt) instruction, which restored PC and PSW as of just before the processor granted the interrupt.

If a bus request were made in error and no device responded to the bus grant, the processor timed out and performed a trap that would suggest bad hardware.

Memory Management

The PDP-11's 16-bit address space can address 64 KBytes. By the time the PDP-11 yielded to the VAX, 8-bit bytes and hexadecimal notation (as opposed to octal) were becoming standard in the industry; however, numeric values on the PDP-11 always use octal notation, and the amount of memory attached to a PDP-11 is always stated as a number of words. The basic logical address space is 32K words, but the high 4K of physical address space (addresses 1600008 through 1777778 in the absence of memory management) are not populated because input/output registers on the bus respond to addresses in that range.

Therefore, a fully expanded PDP-11 had 28K words, or 56 KBytes. The processor reserves low memory addresses for two-word vectors that give a program counter and processor status word with which to begin a service routine. When an I/O device interrupts a program, it places the address of its vector on the bus to indicate which service routine should take control. The lowest vectors are service routines to handle various types of traps. Traps occur on some program errors, such as an attempt to execute an undefined instruction; and also when the program executes an instruction such as BPT, EMT, IOT, or TRAP to request service from the operating system.

Memory Expansion

During the life of the PDP-11, the 16-bit logical address space became an increasing limitation. Various techniques were used to work around it. Later PDP-11 processors included memory management options to support virtual addressing. The physical address space was extended to 18 or 22 bits; allowing up to 256 KBytes or 4 MBytes of RAM. The logical address space (that is, the address space available at any moment without changing the memory mapping table) remained limited to 16 bits. Some models, beginning with the PDP-11/45, can be set to use 32K words (64 KB) as the instruction space for program code and a separate 32K words of data space. Some operating systems; Unix since edition V7, and RSX11-M+—relied on this feature. Programming techniques, such as overlaying a block of stored instructions or data with another as needed, can conceal paging issues from the application programmer.

Optional Instruction Sets

  • Extended Instruction Set (EIS) - The EIS was an option for 11/35/40 and 11/03, and was standard on newer processors.
    MUL, DIV multiply and divide integer operand to register pair ASH, ASHC arithmetic - shift a register or a register pair. For a positive number it will shift left, and right for a negative one. On the 11/03 the EIS was implemented through a microcode 40-pin chip added to one of the spare sockets on the processor board.
  • Floating Instruction Set (FIS) - The FIS instruction set was an option for the PDP-11/35/40 and 11/03. Instructions FADD, FSUB, FMUL, FDIV only for single-precision operating on stack addressed by register operand
  • Floating Point Processor (FPP) - This was the optional floating point processor option for 11/45 and most subsequent models. Implemented full floating point operations on single or double-precision operands, selected by single/double bit in Floating Point Status Register. Single-precision floating point data format predecessor of IEEE 754 format: sign bit, 8-bit exponent, 23-bit mantissa with hidden bit 24.
  • Commercial Instruction Set (CIS) - The CIS was implemented by optional microcode in the 11/23/24, and by an add-in module in the 11/44 and in one version of the 11/74. It provided string and decimal instructions used by COBOL and DIBOL languages.

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