PDP-11/23/24
Introduction
The PDP-11/23 (KDF11-A)
The PDP-11/23 was introduced in 1979 as a successor to the PDP-11/03. The F11 microprocessor was based on dual 40 pin DIP chips. The base processor board was a dual-height KDF11-A CPU card. The memory management was 22 bit (4MB addressing space), but in some revisions (KDF11-A Rev. A) only 18 lines were used. The LSI-11/23 instruction set consisted of 97 standard instructions and 46 optional floating point instructions. The CPU micro-cycle time is 300ns. The KDF11-A module has four 40-pin sockets for the chipset. One is for the DCF11 two-chip hybrid (21-15541AB data path and 23-001C7 control chip), one's for the KTF11 MMU option and one's for the KEF11 floating-point option (another two-chip carrier; the MMU must be installed to use the FPP option). The remaining socket can be used with the CIS option, which spans two sockets wide (so you loose the FPP).
The F11 chipset was also the processor used for the DEC PRO325 and PRO350 computers. The PDP-11/24 is a UNIBUS implementation of the PDP-11/23 PLUS.
The PDP-11/23 PLUS (KDF11-B)
The PDP-11/23 PLUS (11/23+) was introduced in 1981. It used a quad-height KDF11-B CPU module, which had two serial lines and boot PROMs on-board. The boot PROMS contained a software monitor, device bootstraps and diagnostics. Four diagnostic red LEDs on the processor board indicates the results of power-on self-test diagnostics.
For floating-point-heavy applications, the FPF11 can be used. This is a quad-height module that is connected to the KEF11-socket on CPU board with a cable and is based on AMD2901 bit slice processors. The performance is six times of the performance of the KEF11 option (64-bit data path, 17-digit accuracy). Personal note, I remember installing n FPF11 module on a small QBus chassis with an 11/23 CPU and subsequently blowing the power supply. It draws a lot of power.
The memory MMU option could expand memory up to 4MBytes and with parity support. Floating point instructions were implemented in microcode or through the optional hardware FPF11. The 11/23+ offered a standard instruction set of 91 instructions including both single and double word operand instructions that operate with bit, byte, 16-word and multiple word data types.
PDP-11/23 PLUS Features
EIS - Extended Instruction Set. This standard EIS contained four additional instructions which allowed hardware integer multiply and divide and direct implementation of multiple shifting.
MMU - Memory Management Unit. Memory management is a standard feature that provides relocation, segmentation and protection. because the virtual address space is segmented, sections of program and data can be shared, conserving memory space and facilitating large memory applications. Several programs can reside in physical memory simultaneously.
CIS - Commercial Instruction Set. CIS is a microcoded extension for business applications that implements a set of commercial instructions on a variety of data types, including character strings, packed decimals and numeric formats. COBOL and DIBOL make extensive use of CIS to increase both compile and execution speed.
Extended QBus. All communications between the CPU and devices occurs over the QBus. The communications is asynchronous and each device operates at its own speed, maximizing overall system performance. A vectored priority interrupt scheme allowed every device to have its own vector and interrupt service routine. The interrupt scheme eliminates the need for polling. Device priority is a function of electrical proximity to the processor. The higher speed controllers, such as disk controllers, should be placed closer to the processor. Faster data transfers between memory and devices can occur through Direct Memory Access(DMA)thereby freeing the CPU from performing I/O activity. Each device regulates the bus addressing and control signals rather than the processor.
PDP-11/23+ Processor Module
Source: Author
Sources:- Adapted from: Frain Research Group
- Adapted from: Wikipedia PDP-11