PDP-11/45/50/55
Introduction
The PDP-11/45 was introduced in 1972 and was the predecessor for the follow-up 11/50 and 11/55 models. As with other post 11/20 processors, it featured the instruction set in microcode. MSI integrated Circuits were used to achieve a higher performance. Core memory, MOS (dynamic) or MOS (static) memory were options that used a separate memory bus.
This series of PDP-11 models all shared a common CPU: the KB11-A and in later models, the KB11-D. The difference between the two CPUs was whether they worked with the FP11-B or FP11-C Floating Point Processor modules. The FP11 floating point was optional, as was the KT11-C Memory Management Unit (the first implementation of the full PDP-11 Memory Management). The 11/45's 18-bit-address space allowed it to have up to 256Kbytes of main memory. Non-DEC products such as the Able Inc. "ENABLE" allowed use of up to 4MBytes, via an extended UNIBUS.
All models featured the traditional switch based console that began with the 11/20.
Model Differences
- The PDP-11/45 uses a KB11-A or KB11-D central processor and can have either (or both) MOS and bipolar memory.
- The PDP-11/50 uses a KB11-A central processor and solid-state (MOS) memory.
- ThePDP-11/55 uses a KB11-D central processor and bipolar memory.
The PDP-11/45 and 11/50 systems, prior to 1976, were available with a KB11-A central processor, an FP11-B floating point unit and MOS or bipolar memory. With the introduction of a high-performance floating point unit (FP11-C), the KB11-A underwent an extensive revision, generating a new CPU version, the KB11-D. The PDP-11/55 was derived using the KB11-D processor with the advanced FP11-C and the inclusion of bipolar (static) high speed memory.
The PDP-11/50 and PDP-11/55 systems used the same processor family (KB11-A and KB11-D), but were configured with the high-speed MS11 Semiconductor Memory, using 350 nsec MOS or 300 nsec bipolar (static) memory, respectively. The PDP-11/55 was an excellent computational tool for large multi-user, multi-task installations. Some were used in flight simulators, e.g. British Airways 747-200 simulator. It was the fastest of the PDP-11 family.
In many aspects, the PDP-11/55 looked similar to the PDP-11/70 (introduced in February 1975). Although, the PDP-11/70 had a 4MByte memory capacity and cache memory as standard. The 11/55 also has the kernel/supervisor/user operating modes as on the 11/70, but the 11/55 only had an 18-bit memory addressing range. A notable difference is that none of the 11/45/50/55 family featured cache memory!
The PDP-11/45/50/55 had two UNIBUSes, normally joined by a single spaced jumper. The second UNIBUS had no arbitration, and was part of dual-ported fastbus memory. The fastbus memory is an independent high speed data bus internal to the these processors, with up to two solid state memory controllers with each controller having two ports; one for the CPU and the other available for a second UNIBUS where conceivably a high speed DMA device could directly write to the memory. The DMA device on the second bus had to have a UNIBUS priority arbitration system, so you could in fact connect another CPU to it. With the fastbus memory, a second processor could access the memory. The only problem was that with the Unibus A and B split, DMA devices on Unibus A could not see the fastbus memory. One client had a PDP-11/50 and PDP-11/20 set up in such a fashion, with the PDP-11/20 doing high speed A/D sampling and signal averaging using shared memory with the PDP-11/50.
Note: this fastbus, is not the same as the product later marketed by DEC as FASTBUS.
PDP-11/45/50/55 Guides
| Document Name | Order Part No. | Publication Date | Domain |
|---|---|---|---|
| PDP-11/45, 11/50 MOS Memory Troubleshooting Guide | DEC-II-HMSTS-A-D | January 1975 | HW |
| PDP-11/45 Maintenance Reference Manual | DEC-II-HMRMA-A-D | November 1972 | HW |
| PDP-11/45 and PDP-11/50 System Maintenance Manual | DEC-II-H45SM-E-D | October 1974 | HW |
| PDP-11/45, 11/50 and 11/55 System Maintenance Manual | EK-11045-MM-007 | September 1976 | HW |
| PDP-11/45 System Engineering Drawings (A) | NA | 1972 | HW |
| PDP-11/45 System Engineering Drawings (B) | NA | 1972 | HW |
| PDP-11/55 Field Maintenance Print Set | MP00039 | 1976 | HW |
| PDP-11/45/70 Maintenance Course Handout Book | NA | 1978 | HW |
| PDP-11/45, 11/50 and 11/55 System User's Manual | EK-1145-OP-001 | December 1976 | USER |
- Adapted from: Gunkies.org