PDP-11/70

INTRODUCTION

The PDP-11/70 was introduced on March 1975 as a follow-up to the 11/45 architecture. Memory was expanded to 4MBytes using a private memory bus. A 2KByte cache and faster I/O devices connected over a new bus; the MASSBUS. This model still retained the UNIBUS. This model was one of the most powerful minicomputers of it's day (1975) with 50% of the performance of a VAX-11/780. Although DEC Sales estimated they could sell 1,000 systems, incredibly over 10,000 PDP-11/70s were sold.

My exposure to this system was at CAE in the late 1980s. At that time CAE was building a nuclear power generation simulator based on the CANDU reactor for Ontario Hydro. The system that controlled the rods that moderated fission was a PDP-11/70. The simulator included a full blown PDP-11/70! In the early 2000s I met an engineering supervisor from Ontario Hydro who noted that they were still using the PDP-11/70 and noted that you almost had to scour the old folks homes to find anyone who could still program this system.

The Living Computer Museum has a PDP-11/70 that was used at Microsoft by the team that developed MS-Word and the Multiplan spreadsheet application. It ran Microsoft's own variant of Unix (Version 7) known as Xenix. It was retired from Microsoft in 1986.

PDP-11/70 System

ARCHITECTURE

The PDP-11/70 was a medium scale general purpose computer using an enhanced, upwardly-compatible version of the basic PDP-11 architecture. The central processor performed all arithmetic and logical operations required in the system. The KB11-B and KB-11C (later) CPU was implemented in Schottky TTL logic; featuring a 980ns instruction cycle (2.5 MIPS).

System Architecture

Memory Management is standard with the basic computer, allowing expanded memory addressing, relocation, and protection. Also standard is a UNIBUS Map which translates UNIBUS addresses to physical memory addresses. The cache contains 2,048 bytes of fast, bipolar memory that buffers the data from main (core or MOS) memory. Also within the CPU assembly are pre-wired areas for a floating point processor and up to four high-speed I/O MASSBUS controllers.

CPU

The PDP-11/70 CPU performs all arithmetic and logical operations required in the system. It also acts as the arbitration unit for UNIBUS control by regulating bus requests and transferring control of the bus to the requesting device with the highest priority. The central processor contains arithmetic and control logic for a wide range of operations. These include high-speed fixed point arithmetic with hardware multiply and divide, extensive test and branch operations, and other control operations. It also provides room for the addition of the high-speed Floating Point Processor, and high-speed controllers.

Modes

The machine operates in three modes: Kernel, Supervisor, and User. When the machine is in Kernel mode, a program has complete control of the machine. When the machine is in any other mode, the processor is inhibited from executing certain instructions and can be denied direct access to the peripherals on the system. This hardware feature can be used to provide complete executive protection in a multiprogramming environment.

The central processor contains 16 general registers which can be used as accumulators, index registers, or as stack pOinters. Stacks are extremely useful for nesting programs, creating re-entrant coding, and as temporary storage when a Last-In/First-Out structure is desirable. One of the general registers is used as the PDP-11/70's program counter. Three others are used as Processor Stack Pointers, one for each operational mode. The CPU performs all computation and logic operations in a parallel binary mode through step-by-step execution of individual instructions.

Floating Point

The KB11C floating point option is a supplemental instruction set for performing single and double-precision floating point arithmetic operations and floating-integer conversion in parallel with the CPU. The floating point processor provides speed and accuracy in arithmetic computations. It provides 7 decimal digit accuracy in single-word calculations and 17 decimal digit accuracy in double-word calculations. Floating point calculations take place in the FPP's six 64-bit accumulators. The 46 floating point instructions include hardware conversion from single- or double-precision floating point to single- or double precision integers.

MEMORY

The PDP-11/70 system had an expanded Internal implementation of the PDP-11 architecture for greatly improved system throughput. The memory is on its own high data rate bus. The internal high-speed I/O controllers for mass storage devices have direct connections through the cache to memory for transferring data (using the cache only for timing purposes). The processor has a direct connection to the cache memory system for very high-speed memory access.

This system uses 22 bits for addressing physical memory. This represents a total of 4 million byte locations. Of the 4 million byte locations possible with the 22-bit address, the top 256K are used to reference the UNIBUS rather than physical memory.

Early models shipped with the MJ11 core memory. Later models used the MK11 MOS semiconductor (dynamic RAM) memories.

ECC and Parity

ECC and Parity are used extensively in the to ensure the integrity of information. Parity for both data and addresses is generated on transfers to memory and is checked on all transfers from memory. Registers are provided within the CPU to provide information on the location of ECC errors, types of errors, and other relevant information so that software can respond to the situation, take corrective action, and log the occurrence of errors.

ECC Operation

The error correcting code, which is employed in MOS memory, will detect and correct single-bit errors in a word, as well as detect double bit errors in a word. Where a double-bit error is detected, the processor is notified, as happens with a parity error. The process of checking is accomplished by combining the bits in a number of unique ways, so that parity, or check bits, are generated for each unique combination and stored along with the data bits. The memory word length is extended to store these unique bits. When memory is read, the data word is again checked, and check bits are regenerated and compared with the check bits stored with the word. If they match, the word is sent on to the processor. If they don't match, an error exists, and the syndrome bits are created and decoded to determine which data bit is in error. The bit in error is then corrected and sent on to the processor.

Memory Expansion

When expanding an MK11-B memory box with MK11-C memory arrays (newer memories), an ample number of slots must exist in the memory box, and all 16 slots may be utilized to realize a maximum capacity of 3.8 Mb. When expanding an MK11-C memory box with an MK11-C memory array, only 14 of the 16 slots may be filled with MK11-C memory, for a total of 3.5 MByes of interleaved memory.

The H960 cabinet will hold two MK11-C MOS memory boxes. If more than two MOS memory boxes are required, an additional cabinet will be needed to accommodate space for the additional memory box

Option	Capacity	Description
MK11-CA/CB	512 KBytes	MOS/ECC with Box
MK11-CC/CD	512 KBytes	MK11-CA/CB with H960 cabinet
MK11-CE	512 KBytes	MOS Memory Expansion
MK11-CF	1MBytes	MOS Memory Expansion
MK11-CG/CH	1MBytes	MOS/ECC with Box

CACHE

The PDP-11/70 featured a 2KByte, 300 nsec 2-way set associative cache, connected to a FastBus high-speed memory interface. The cache size was a carefully developed approach, backed by extensive program simulations to determine hit statistics.

PDP-11/70 Cache System

The cache memory is a very high-speed memory that buffers data between the processor and main memory. The cache is completely transparent to all programs; programs are treated as if there were one continuous bank of memory.

Whenever a request is made to fetch data from memory, the cache circuitry checks to see if that data are already in cache. If they are, then they are fetched from there and no main memory read is required. If the data are not already in cache memory, four bytes are fetched from main memory and stored in the cache, with the requested word or byte being passed directly to the CPU. When a CPU request is made to write data into memory, it is written both to the cache and to main memory to insure that th stores are always updated immediately.

I/O

The UNIBUS remains the primary control path in the PDP-11/70 system. It is conceptually identical with other PDP-11 systems; the memory in the system still appears to be on the UNIBUS to all UNIBUS devices. Control and status information to and from the high speed I/O controllers is transferred over the UNIBUS. This expanded internal implementation of the PDP-11 architecture has no effect on programming.

This system could support up to 4 RH70 MASSBUS controllers. The MASSBUS controllers connected high speed devices such as disk and tape directly to main memory, thereby bypassing the slower UNIBUS.

Sources:

• Adapted from: Wikipedia PDP-11
• Adapted from: Living Computers Museum - PDP-11/70
• Adapted from: hampage.hu, PDP-11 History of a Legend
• Adapted from: Avitech.au - PDP-11/70

Compiled on 07-24-2024 07:44:14