PDP-11/73/83/84/93/94

INTRODUCTION

This family of high performing PDP-11/73/83/84/93/94 systems all used the VLSI J-11 microprocessor (DEC Part no. DCJ11-AC 57-19400-09). This was DEC's fourth and its last PDP-11 microprocessor design.

J-11 Microprocessor

This processor chip operated at 18 MHz and provided higher levels of performance over previous microprocessor based models. The J-11 microprocessor featured 16 bit I/O, 32 bit internal data paths, addressing up to 4 MBytes and on-chip memory management. The complete PDP-11 instruction set including the Extended Instruction Set (EIS) was included. Cache consisted of 8KByes of direct mapped memory. This CPU design exceeded the performance and functionality of DEC's larger PDP-11/70. The J-11 was also used on the Professional Series PRO 380 desktop computers; some of which were also used as system consoles on the VAX 8000 series computers.

The J-11 project was co-developed with Harris Semiconductor. Bob Subpnik at DEC was the project leader. Harris Corp. (Intersil Semiconductor Division) manufactured the two dies on the J-11 ceramic CPU. These consisted of a data path chip and a control chip in ceramic lead-less package mounted on a single ceramic hybrid 60 pin DIP package. The DC335 data chip (Harris D4-6901-5) held 40 thousands transistors, while the DC334 control chip (Harris D4-6900-5) had 80 thousand transistors. By comparison the Intel 80486 (1989) CPU die help approximately 1.2 million transistors.

J11 chip with exposed dies

The control chip incorporated a control sequencer and a microcode ROM. An optional separate floating-point accelerator (FPA) chip could be used, and was packaged in a standard 40-pin DIP. The data path chip and control chip were fabricated in a CMOS process (the first DEC CMOS processor) while the FPA was fabricated by Digital in their "ZMOS" NMOS process. Microcode-based floating point was standard but a floating point accelerator was available as a separate chip on the processor board. The CPU design was also intended to support multiple control chips to allow implementation of additional instructions such as the Commercial Instruction Set (CIS), but no such control chips were ever offered.

The DC334 Control Chip performed the following functions:

• Interrupt logic
• Abort logic
• Initial decode PLA (Q logic)
• External interface sequencer
• Instruction pre-fetch logic
• Micro sequencer
• Next address logic
• Micro subroutine stack
• Microcode ROM

The DC335 Data Chip implemented memory management and instruction execution including the following functions:

• Byte swap
• Conditional branch logic
• Memory management logic
• Memory management registers
• Address translation logic (22 bit)
• Protection logic
• External interface sequencer
• Instruction pre-fetch logic
• Execution unit
• PDP-11 architectural general registers (16 bit): dual register set, three stack pointers
• Processor status word (PSW)
• Microcode temporary registers (32 bit)
• Full function arithmetic/logic unit (32 bit)
• Single bit shifter

Initial chip fabrication was problematic. The first batch of microprocessors could barely run at 1.25MHz. After many revisions the clock rate was increased to 3.75MHz, then 4.5MHz before achieving the target design spec of 18MHz. Rumors had it that the actual target clock speed was 20MHz but was only achieved with the latest J-11 microprocessors. The initial problems with the J-11 resulted in two field recalls of the processor.

J-11 Pin Assignment

A clone of the J-11 was manufactured in the Soviet Union under the designation KN1831VM1.

PDP-11/73

The PDP-11/73 (KDJ11-A) was introduced in 1993. It used the DEC J-11 chip set and a Q-Bus, with a clock speed of 15.2 MHz. The KDJII-A (M8192 dual width, KDJ-11D M7554 quad width) is a dual-height processor module for LSI-II type bus systems. It was designed for use in high-speed, real-time applications and for multiuser, multitasking environments. The KDJ11-A module executes the complete PDP-11 integer and FP-11 floating-point instruction sets. Full 22-bit memory management was provided for both instruction references and data references in three protection modes - kernel, supervisor, and user. The KDJ11-A module was fully downward compatible with older PDP-11 models which had 18-bit memory management or no memory management.

The processor relied on memory being on the QBus, it didn't have a private memory inter-connect memory interface as did the PDP-11/83/93 models. As a result its performance is slower than other J-11 models due to having to rely on the slower QBus based dynamic RAM.

PDP-11/73 (M8192)

The KDJ ll-A module supports console emulation (micro octal debugging tool or ODT). This allows users to interrogate and write main memory and CPU registers as if a console switch panel and display lights were available.

Self-diagnostic LEDs are provided on the KDJ11-A module and indicate the status of the module and system when the module is powered-up. The LEDs aid in troubleshooting module failures.

PDP-11/83/84

The PDP-11/8X (KDJ11-B, M8190) series was introduced in 1985. A Q22 but interface supports block-mode DMA and up to four MBytes of Error Correcting (ECC) physical memory using 256KByte dynamic RAM. A Private Memory Interconnect (PMI) bus supports high-speed data transfers between the CPU and memory, an approach also used on the PDP-11/70 and the MicroVax II.

PDP-11/83/84 Q22 Board

In the picture above, the floating point unit is the 40 pin DIP to the right of the J-11 chip. The other two large ceramic chips are the system and cache controller gate array and the DMA controller gate array.

The 11/84 model is basically the 11/83 with a UNIBUS adapter so that client investment in UNIBUS peripherals can be maintained.

PDP-11/93/94

The PDP-11/9X (KDJ11-E) series was introduced in 1990. The MicroPDP-11/93 computer was fully hardware compatible with Q-bus PDP-11 computer systems and was available as a rack mountable or freestanding computer. The PDP-11/94 computer is hardware compatible with the UNIBUS-based PDP-11/84 computer, which it replaced. Both models featured 140 percent of the performance of the top-line PDP-11 computers they replaced. These, systems supported six basic operating systems, and a variety of high-level programming languages, including FORTRAN, COBOL, Pascal, BASIC, and C.

The PDP-11/93 system provided hardware compatibility with Q-bus processors having 22-bit addressable backplanes and had the same physical dimensions as its predecessors, making it easy to use as a replacement in existing configurations. As with the 11/84, the 11/94 was basically an 11/93 with a UNIBUS adapter so that clients could retain their investment in UNIBUS peripherals.

On-board memory was available in 2MByte and 4MByte configurations. A 2MByte PDP-11/94 rack mount base system could be purchased for $13,500.00 USD. A 2MByte upgrade board for the PDP-11/93/94 was priced at $8,500.00 USD (1990 prices). One article refers to main memory being static RAM (70ns access time) instead of dynamic thereby providing a performance increase. Basically main memory with the same speed as the cache.

The 11/93/94 systems were one of the most compact and powerful PDP-11 lines, including on-board memory, the 18MHz J-11 processor and floating point; all on one quad size board. Later J-11 microprocessors could reach 20MHz operation; providing slightly faster performance over previous processors.

GUIDES

Document Name	Order Part No.	Publication Date	Domain
KDJ11-A CPU Module User's Guide	EK-KDJ1A-UG-002	June 1986	HW
Microcomputer Products Handbook	N/A	1985	HW
PDP-11/94-E System User and Maintenance Guide	EK-PDP94-MG-001	1990	HW
MicroPDP-11/83 - The Most Powerful 16-bit Q-bus Supermicrosystem (brochure)	N/A	N/A	Sales
PDP-11/84 (brochure)	N/A	N/A	Sales

Sources:

• Adapted from: Wikipedia DEC J-11
• Adapted from: S100 Computers - the PDP-J11 S100 Bus CPU Board
• Adapted from: CPU Museum - DEC Architectures
• Adapted from: niconiconi's blog - vintage chip collection
• Adapted from: CPU Galaxy - DEC & Alpha CPUs

Compiled on 07-24-2024 07:45:52