VAX 11/750

Introduction
The VAX-11/750 was a slower, more compact version of the VAX-11/780. It was introduced on October 1980 and nicknamed Comet by DEC. The 750 was a more compact, lower-performance TTL Bipolar gate array–based implementation of the VAX architecture. Unlike the 780, the 750 could run from a single phase power. The use of gate arrays decreased power consumption and increased reliability compared with the VAX-11/780. The VAX-11/751 was a ruggedized rack mounted version of the 750.

Over 90% of the VAX architecture was implemented in the gate arrays, and there was a lot of them, 95 in a complete system with the floating point accelerator (28 arrays). The CPU and Memory controller used 55 while the Massbus (I/O) used an additional 12 gate arrays. The 95 gate arrays though replaced hundreds of discrete TTL chips. And as a further simplification they were all the same gate array. Each gate array contained 400 (2 transistor) 4 input NAND gates, and 44 transceiver gates (one for each I/O pin).

They were factory programmed to be any one of the 39 different types needed for a 11/750. Each was packaged in a 48 lead DIP-like ceramic flat pack. Max power dissipation was 2W per ship and they required only two power supplies (5V and 2.5V). Die size was a relatively small 33.8mm2. This allowed for near commodity manufacturing, further lowering prices. Each one had an aluminum heat sink over it and held in place with a simple wire clip.

The heart of the Comet was the Data Path Module. This consisted of the scratch pad registers, control logic, the ALU, and the super rotator (a 32-bit rotator which handling all rotates and bit shifting). The ALU was built using 8 identical gate arrays. Each was configured as a 4-bit processor slice (much like an AMD Am2901, which later VAX implementations would use. Each gate array was labeled for easy maintenance if needed. With only 400 gates to work with, the VAX architecture had to be divided over many arrays, it was still an improvements over discrete TTL which offers only a handful of gates per chip.

The 22 gate arrays that make up the Comet Data Path were:

• 608B – ALP – 4-bit Arithmetic/Logic Processor slice (x8)
• 610B – CCC – Condition Code Chip
• 612B – CLA – Carry Look Ahead
• 613B – SRM – 8-bit Super Rotator slice (x4)
• 614C – SRK – Super Rotator Control
• 615B – ALK – ALP Control
• 616C – SPA – Scratch pad Address Control
• 617C – SAC – Service Arbitration and Clock
• 620A – TOK – Interval Timer
• 621C – MSQ – Micro-Sequence
• 622B – IRD – Instruction Register Decode
• 629C – PHB – Status/next instruction logic

Memory Interconnect Module (18 Gate Arrays):

• 607B – MDR – Memory Data Registers (x8)
• 609E – ADD – Address Chips (x4)
• 623C – CAK – Cache Control Chip
• 624E – PRK – Pre-fetch Control
• 625B – ACV – Access Violation
• 626B – ADK – Address Control
• 627B – CAK – CPU Memory Interconnect Control
• 628B – UTR – Microtrap Monitor

Unibus Interface Module (8 Gate Arrays):

• 611B – CON – Console interface (x2)
• 618C – UDP – Unibus Data Path (x4)
• 619D – UCN – UPD Control
• 630B – INT – Interrupts

SPECIFICATIONS

CPU CPU Module: KA750 Number of Processors: 1 CPU Technology: AMD AM2901 bit slice units CPU Cycle Time: 320ns (3.125MHz) Writable Control Store: 1K X 80-bit words Control Store: 6K X 80-bit words Cache: 4KBytes PDP-11 Compatibility Mode: YES Console Boot Processor: CPU Console Storage Device: TU58 MEMORY Maximum Memory: 8MBytes with an L0011 memory controller or up to 14MBytes with an L0022 memory controller. Memory uses 16KBit , 64KBit and 256Kbit dynamic RAMs. Address Lines: 24 Memory Checking: 7-bit ECC I/O INTERFACES UNIBUS: 3 at 1.5MB/s MASSBUS: 2 at 2MB/s CI: 1 LAN Support: optional PERFORMANCE VUPS: 0.6 Source: Text adapted from gunkies.org and cpushack.com .

VAX-11/750 Modules

L0002 contains the arithmetic logic, rotator logic, main registers and a micro sequencer.

L0003 contain the address logic, translation buffers, cache memory and data routing and alignment logic.

L0006 contains the 8085 microprocessor performs very low level diagnosing of the machine locally or remotely.

L0007 interfaces with various Massbus disks or tape devices.

L0008 is an upgrade to the L0005 board. This module contain the 6k x 80 bit control store in bipolar PROMs. But also 1k x 80 patch control store. The ROM based control store can be patched with the contents of the RAM if a flag RAM is set. This board also has the main clock generator. A 18.75 MHz clock generator which is divided by 3 to produce a 160 ns clock and then further to a 320 ns clock used by the micro sequencer. All clock division takes place on the DPM (L0002) module so the PCS module only contains the clock oscillator itself.

L0011 is a controller for memory boards with 16Kbit dynamic memory chips.

L0022 is a controller for memory boards with 256Kbit dynamic memory chips.

Sources:

• gunkies.org
• wikipedia.org
• cpushack.com
• datormuseum.se