VAX 9000

Introduction

The VAX 9000 is a discontinued family of mainframes developed and manufactured by Digital Equipment Corporation (DEC) using custom ECL-based processors implementing the VAX instruction set architecture (ISA). Equipped with optional vector processors, they were marketed into the supercomputer space. As with other VAX systems, they were sold with either the VMS or Ultrix operating systems. The VAX 9000 family extended the range of the VAX family into the high-end of performance by offering different configurations providing performance levels between 30 and 108 VUPs.

History

The systems trace their history to DEC's 1984 licensing of several technologies from Trilogy Systems, who had introduced a new way to densely pack ECL chips into complex modules. Development of the 9000 design began in 1986, intended as a replacement for the VAX 8800 family, at that time the high-end VAX offering. The initial plans called for two general models, the high-performance Aquarius using water cooling as seen on IBM systems, and the midrange-performance Aridus systems using air cooling. During development, engineers so improved the air cooling system that Aquarius was not offered; the Aridus models were "field-upgradeable" to Aquarius, but they did not offer it.

The 9000 was positioned within DEC as an "IBM killer", a machine with unmatched performance at a much lower price point than IBM systems. DEC intended the 9000 to allow the company to move back into the mainframe market, which it had abandoned starting in 1983, as it watched the low end of the computer market being taken over by ever-improving IBM compatible personal computer systems and the new 32-bit Unix workstation machines.

The company invested an estimated $1 billion in the development of the 9000, in spite of considerable in-company concern about the concept in the era of rapidly improving RISC performance. Production problems pushed back its release, by which time these fears had come true and newer microprocessors like DEC's own NVAX offered a significant fraction of the 9000's performance for a tiny fraction of the price.

Roughly four dozen systems were delivered before production was discontinued; a massive failure. One representative example CPU sits in storage at the Computer History Museum (Mountain View, California), but not on public display. Another is in storage at the Large Scale Systems Museum (Kensington, Pennsylvania).

Trilogy Systems

A related ECL issue was inter-chip wiring proliferation proportional to the massive pin count increase required by modern machines’ address space growth. In 1980, Gene Amdahl formed Trilogy Systems to solve problems in high-performance ECL-based mainframe production. Trilogy's developments included a new inter-chip connection system using copper conductors embedded in polyimide insulation to produce a thin-film with extremely dense wiring.

In 1984, DEC licensed parts of Trilogy's technologies and began development of practical versions of these concepts at their Hudson Fab. This was the birth of the 9000 project. In contrast to Trilogy's goal of introducing their own plug-compatible mainframes and competing with IBM directly, DEC would use similar technology to produce a VAX outperforming IBM's offerings at a lower price point. Trilogy's wiring technologies were used to create card-sized "multi-chip units" (MCUs) working together like earlier multi-card CPU designs. In the final design, 13 MCUs formed the CPU.

Initially, the system required water cooling to meet its performance goals, leading to the codename Aquarius, the water-bearer. During development, a newly introduced air cooling system replaced water cooling. The air-cooled version was codenamed Aridus, for "dry".

IBM's VAX Killer

While development was ongoing, in late 1988 IBM introduced its AS/400 systems, a new mid-range line that was much more cost-competitive than previous offerings. DEC's price advantage was seriously eroded, and their formerly rapid market growth ended almost immediately. IBM would ultimately generate roughly $14 billion in annual revenue from the line, which was more than DEC's entire company income.

Meanwhile, Sun was introducing their SPARC microprocessor which allowed desktop machines to outperform even the fastest of DEC's existing machines. This eroded DEC's value in its other traditional market of Unix systems. With the company being squeezed in the low and midrange, the 9000 became the company's main focus; they referred to it as the "IBM killer".

Public Release

DEC formally announced the 9000's in October 1989, claiming at the time that it would ship "next spring." Comparing it to a low-end IBM 3090, IBM's flagship mainframe, DEC positioned the machine for transaction processing and high-end database systems. Five systems were announced, from $1.2 to $3.9 million, spanning a performance range from 30 to 117 times that of the 11/780.

The development of the 9000 eventually ran to about $3 billion. Slated for release in 1989, delays in the chip manufacturing delayed it by a year, and further delays in building the complete machine meant only tiny numbers were delivered in 1990. The systems were plagued with problems and required constant maintenance in the field. By 1991 the company had an order book of only 350 systems. At $1.5 million per machine, the system had recouped only 25% of the development costs, excluding actual manufacturing.

In February 1991, they announced a low-end version, the Model 110 at $920,000, appealing to customers looking for CPU power without the need for extensive storage or other options.

Meanwhile, the engineering team's predictions about the relentless march of CMOS proved true. By 1991, the NVAX was also on the market, offering roughly the same performance for a tiny fraction of the cost and size. At lower performance settings the same design was available in desktop form, outperforming all previous VAX machines. The 9000 managed not only to lose billions of dollars, but also led to the ending of several much more promising designs.

Hardware Failures

Adding to the woes, in early 1992 it was reported that installed systems had begun to suffer a series of hardware failures that appeared to start in the second half of 1991. A study suggested 37% of the installed systems suffered "hard failure", mostly on the 9420 models. A follow-up survey gave the system high marks for service and compatibility with other DEC systems, but low marks for reliability and cost.

System Architecture

The VAX 9000 was a multiprocessor and supported one, two, three or four CPUs clocked at 62.5 MHz (16ns cycle time). The system was based around a crossbar switch in the system control unit (SCU), to which the one to four CPUs, two memory controllers, two input/output (I/O) controllers and a service processor connected. I/O was provided by four Extended Memory Interconnect (XMI) buses.

Each CPU was implemented with 13 Multi-Chip Units (MCUs), with each MCU containing several emitter-coupled logic (ECL) macrocell arrays which contained the CPU logic. The gate arrays were fabricated in Motorola's "MOSAIC III" process, a bipolar process with a drawn width of 1.75 micrometres and three layers of interconnect. The MCUs were installed into a CPU planar module, which accommodated 16 MCUs and was 24 by 24 inches (610 mm) in size.

The VAX 9000's CPU was coupled with a vector processor with a maximum theoretical performance of 125 MFLOPS. The vector processor circuitry was present in all units shipped and disabled via a software switch on units sold 'without' the vector processor. The vector processor was referred to as the V-box, and it was Digital's first ECL implementation of the VAX Vector Architecture. The design of the vector processor began in 1986, two years after development of the VAX 9000 CPU had begun.

The V-box implementation comprised 25 Motorola Macrocell Array III (MCA3) devices spread over three multichip units (MCUs), which resided on the planar module. The V-box was optional and was field-installable. The V-box consisted of six subunits: the vector register unit, the vector add unit, vector multiply unit, vector mask unit, vector address unit and the vector control unit.

The vector register unit, also known as the vector register file, implemented the 16 vector registers defined by the VAX vector architecture. The vector register file was multi-ported and contained three write ports and five read ports. Each register consisted of 64 elements, and each element was 72 bits wide, with 64 bits used to store data and 8 bits used to store parity information.

SID Scalar and Vector Processor Synthesis

SID (Synthesis of Integral Design) was a logic synthesis program used to generate logic gates for the VAX 9000. From high-level behavioral and register-transfer level sources, approximately 93% of the CPU scalar and vector units, over 700,000 gates, were synthesized.

SID was an artificial intelligence rule-based system and expert system with over 1000 hand-written rules. In addition to logic gate creation, SID took the design to the wiring level, allocating loads to nets and providing parameters for place and route CAD tools. As the program ran, it generated and expanded its own rule-base to 384,000 low-level rules. A complete synthesis run for the VAX 9000 took 3 hours.

Initially it was somewhat controversial but was accepted in order to reduce the overall VAX 9000 project budget. Some engineers refused to use it. Others compared their own gate-level designs to those created by SID, eventually accepting SID for the gate-level design job. Since SID rules were written by expert logic designers and with input from the best designers on the team, excellent results were achieved. As the project progressed and new rules were written, SID-generated results became equal to or better than manual results for both area and timing. For example, SID produced a 64-bit adder that was faster than the manually-designed one. Manually-designed areas averaged 1 bug per 200 gates, whereas SID-generated logic averaged 1 bug per 20,000 gates.

After finding a bug, SID rules were corrected, resulting in 0 bugs on subsequent runs. The SID-generated portion of the VAX 9000 was completed two years ahead of schedule, whereas other areas of the VAX 9000 development encountered implementation problems, resulting in a much delayed product release. Following the VAX 9000, SID was never used again.

Models

The VAX 9000 line featured three models:

• Model 110 - this was an entry-level model with the same performance as the Model 210 but had a smaller memory capacity and was bundled with less software and services. On 22 February 1991, it was priced from US $920,000, and if fitted with a vector processor, from US $997,000.
• Model 210 - model 210 was an entry-level model with one CPU that could be upgraded. If a vector processor was present, it was known as the VAX 9000 Model 210VP.
• Model 4X0 - this model was a multiprocessor capable model, the value of "X" (1, 2, 3 or 4) denoting the number of CPUs present. These models supported the vector processor, with one vector processor supported per CPU. A maximal configuration had 512 MB of memory. The number of I/O buses supported varied, with the Model 410 and 420 supporting 2 XMI, 10 CI and 8 VAXBI; while the Model 430 and 440 supported 4 XMI, 10 CI and 14 VAXBI.

Prologue

By 1991, industry observers were describing the 9000 as "stalled" and "disappointing". In October 1991, DEC announced that the division would be reorganized as the Production System Business Unit, along with cuts on the prices of the current 9000 models of 30%, and 38% on its server software. They also announced three new models based on CMOS chips, the 9X15, 9600 and 9800, none of which shipped. They also announced that existing users of the 9000 would be offered a discounted upgrade path to new DEC Alpha-based systems.

Further Reading

The VAX 9000 was a complex system using state of the art ECL technology. The reader is encouraged to look into the documents below for more detail. The Aquarius/Aridus Preliminary information Package document below is a detailed description of the internal architecture of the VAX 9000. It is a planning document describing what the new processor architecture will be and its implementation. The VAX 9000 Systems Introduction is also a good read to best understand this system.

Guides

Document Name	Order Part No.	Publication Date	Domain
Aquarius/Aridus Preliminary Information Package	*Restricted*	26 May 1988	HW
VAX 9000 Console Command Description	EK-9000C-CD-001	May 1990	User
VAX 9000 System Introduction	EK-9000C-SI-001	May 1990	User
VAX 9000 XJA Technical Description	EK-KA90A-TD-001	May 1990	HW
VAX 9000 IBox Technical Description	EK-KA90A-TD-001	May 1990	HW
VAX 9000 SCU Technical Description	EK-KA90J-TD-001	May 1990	HW
VAX 9000 Clock Subsystem Technical Description	EK-KA90K-TD-001	May 1990	HW
VAX 9000 Power System Technical Description	EK-KA90P-TD-001	May 1990	HW
VAX 9000 System Technical Description	EK-KA90S-TD-001	May 1990	HW

Sources:

• wikipedia.org