VAX 8XX0
VAX 8200/8250/8300/8350
The VAX 8200 and VAX 8300, code named Scorpio, were mid-range minicomputers introduced on
29 January 1986. The VAX 8300 was a dual-processor variant of the VAX 8200 and,
with the VAX 8800 introduced on the same date, were among the first multiprocessor VAX computers.
These were the slowest machines (1.2-1.3 VUPs) featuring the VAXBI bus.
Unlike the 88xx and 85xx series, which were based on ECL technology, they were based on ZMOS technology.
They used the KA820 CPU module containing a V-11 microprocessor operating at 5 MHz (200ns cycle)
and supported a maximum of 128MB of ECC memory. It featured one VAXBI bus and support for an optional Unibus.
The VAX 8250 and VAX 8350 were faster models of the 8200 and 8300 introduced in early March 1987. They used the KA825 CPU module containing a V-11 microprocessor operating at 6.25 MHz (160ns cycle).
VAX 8500/8530/8550
The VAX 8500, code-named Flounder, was a lower-performance variant of the VAX 8550. It had limited throughput (16 MB/sec), slower CPU (3-6 VUPs), and limited expansion options. NOPs were introduced into its microcoded instruction set to purposefully limit performance by adding these time killing instructions. The VAX 8530, code-named Skipjack, was an upgraded VAX 8500 with the firmware NOPs removed for improved performance. It was introduced in early March 1987. The VAX 8550, also code-named Skipjack, was introduced in early August 1986. It was similar to the VAX 8700, but could not be upgraded to a VAX 8800.
VAX 8600
The VAX 8600, code-named Venus, introduced in October 1984, was the successor of the VAX-11/785. It was originally to be named VAX-11/790, but was renamed before launch. The VAX 8600 was a successful model and at the time was the best selling high-end VAX. It was succeeded by the VAX 8800 family in 1987. The VAX 8600 has a CPU with an 80ns cycle time (12.5 MHz) implemented with emitter coupled logic (ECL) macrocell arrays (MCAs).
The CPU consists of four major logical sections, the E Box, F Box, I Box and M Box. The E Box executes all instructions, including floating-point instructions through microcode. It has an arithmetic logic unit (ALU) and barrel shifter. The F Box, or floating point accelerator (FPA), is an optional feature that accelerates floating-point instructions as well as integer multiplication and division. It is a two-module set consisting of an adder module and multiplier module. The adder module contains 24 macrocell arrays while the multiplier module contains 21. The I Box fetches and decodes instructions. The M Box controls the memory and I/O, translates virtual addresses to physical addresses and contains a 16KB data cache.
The CPU used 145 MCAs. These are large scale integration devices fabricated by Motorola in their 3 micrometer (um) MOSAIC bipolar process. They are packaged in 68-pin leadless chip carriers or pin grid arrays and are mounted onto the printed circuit board in sockets or soldered in place. An additional 1,100 small scale integration (SSI) and medium scale integration (MSI) ECL logic devices are used. These ICs are spread out over 17 modules plugged into a backplane.
The VAX 8600 supports 4 to 256MB of ECC memory. It has eight slots on the backplane for memory modules. The system originally used 4 MB memory modules populated by 256 KBit metal oxide semiconductor (MOS) RAMs, which limits capacity to 32 MB. Modules with larger capacities were introduced later. The memory is controlled by the M Box, which also provides the memory array bus used to access the memory. This dedicated bus, which has an 80ns (12.5 MHz) cycle time, contributes to the improved performance the VAX 8600 has over the VAX-11/780, which access memory via the Synchronous Backplane Interconnect (SBI) shared with I/O devices.
I/O is provided by the SBI. The VAX 8600 features one SBI but could be configured with two. The SBIs are provided by SBI adapters that interface the SBI to an internal adapter bus connected to the M Box. Each SBI has 16 slots for I/O devices, although only 15 are usable as one slot is reserved for the SBI adapter. With one SBI, that SBI has a bandwidth of 13.3 MB/s. With two SBIs, they have a total bandwidth of 17.1 MB/s. The adapter bus that interfaces the SBIs to the M Box has a bandwidth of 33.3 MB/s. Unibus and Massbus are also supported, provided by adapters that plug into the SBI.
The VAX 8600 I/O cabinet contains a PDP-11 computer serving as the console, a Unibus card cage and provisions for mounting disk drives.
VAX 8650
The VAX 8650, code-named Morningstar, was a faster version of the VAX 8600 introduced on 4 December 1985. It was originally to be named VAX-11/795, but was renamed before launch. Notably, the VAX 8600 is the last VAX to be 100% compatible with the VAX-11/780 and VAX-11/785, to have the PDP-11 compatibility mode, and to use the SBI also used by the VAX-11/78x. The CPU had a 55ns cycle time (18.18 MHz).
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