PDP-8/S
Introduction
The PDP-8/S was introduced in 1966 at a cost of $10,000.00. DEC meant this to be a low cost replacement for the original PDP-8 minicomputer. To do so, they created a serialized architecture, which reduced the part count, and hence cost. However, it resulted in one of the slowest PDP-8 processors. It didn't have a long lifetime and was discontinued after selling only 1024 units being superseded but newer faster and lower cost PDP-8s.
This model was constructed with transistors packaged on DEC FLIP CHIP modules. It could perform an addition to the accumulator in 64 micro seconds. Parity bit on the main memory was standard, not optional as in some other models. Memory could be expanded to 32K words with a read speed of 8 microseconds.
PDP-8/S System
Source: Wikipedia
PDP-8/S Options Summary
| Option | Description |
|---|---|
| DB8S | Data Break, needed for data break on the I/O bus. |
| MC8S | Memory Extension Control, needed to support more than 4K words of memory. |
| MM8S | Memory Module. |
| ME8S | Memory Extension, holds two MM8S. |
PDP-8/S Documents
| Document Name | Order Part No. | Publication Date | Domain |
|---|---|---|---|
| PDP-8/S User Manual | F-85S_PDP-8S | 1986 | HW |
| PDP-8/S Maintenance Manual | F-87S_8S | October 1970 | HW |
PDP-8/S Chassis View
Chassis view with the core memory block clearly visible on the mid left of the chassis.
Source: http://www.corestore.org/8s.htm
Module layout. These are transistor based Flip-Chip modules. You can imagine with this many connectors and discrete components that the mean time before failure (MTBF) must have been high.
Source: http://www.corestore.org/8s.htm
Sources:- Adapted from: https://en.wikipedia.org/wiki/PDP-8