PDP-8 Instruction Set

Introduction

The three high-order bits of the 12-bit instruction word (labelled bits 0 through 2) are the operation code.

• For the six operations that refer to memory, bits 5 through 11 provide a 7-bit address.
• Bit 4, if set, says to complete the address using the 5 high-order bits of the program counter (PC) register, meaning that the addressed location was within the same 128 words as the instruction.
• If bit 4 is clear, zeros are used, so the addressed location is within the first 128 words of memory.
• Bit 3 specifies indirection; if set, the address obtained as described so far points to a 12-bit value in memory that gives the actual effective address for the instruction; this allows operands to be anywhere in memory at the expense of an additional word. The JMP instruction does not operate on a memory word, except if indirection is specified, but has the same bit fields.

Memory Organization

This use of the instruction word divides the 4,096-word memory into 128-word pages; bit 4 of the instruction selects either the current page or page 0 (addresses 0000–0177 in octal). Memory in page 0 is at a premium, since variables placed here can be addressed directly from any page. (Moreover, address 0000 is where any interrupt service routine must start, and addresses 0010–0017 have the special property of auto-incrementing preceding any indirect reference through them.) The standard assembler places constant values for arithmetic in the current page. Likewise, cross-page jumps and subroutine calls use an indirect address in the current page. It was important to write routines to fit within 128-word pages, or to arrange routines to minimize page transitions, as references and jumps outside the current page require an extra word. Consequently, much time was spent cleverly conserving one or several words. Programmers deliberately placed code at the end of a page to achieve a free transition to the next page as PC was incremented.

Basic Instructions

• 000 – AND – AND the memory operand with AC.
• 001 – TAD – Two's complement ADD (a 12 bit signed value (AC) with carry in L).
• 010 – ISZ – Increment the memory operand and Skip next instruction if result is zero.
• 011 – DCA – Deposit AC into the memory operand and clear AC.
• 100 – JMS – JUMP to Subroutine (storing return address in first word of subroutine).
• 101 – JMP – JUMP.
• 110 – IOT – Input/Output Transfer (see below).
• 111 – OPR – Microcoded Operations (see below).

Input-Output Transfer (IOT) Instructions

The PDP-8 processor defined few of the IOT instructions, but simply provided a framework. Most IOT instructions were defined by the individual I/O devices. Bits 3 through 8 of an IOT instruction select an I/O device. Some of these device addresses are standardized by convention:

Device

• 00 is handled by the processor and not sent to any I/O device (see below).
• 01 is usually the high-speed paper tape reader.
• 02 is the high-speed paper tape punch.
• 03 is the console keyboard (and any associated low-speed paper tape reader).
• 04 is the console printer (and any associated low-speed paper tape punch).

Instructions for device 0 affect the processor as a whole. For example, ION (6001) enables interrupt processing, and IOFF (6002) disables it.

Function

• Bits 9 through 11 of an IOT instruction select the function(s) the device performs.
• Simple devices (such as the paper tape reader and punch and the console keyboard and printer) use the bits in standard ways:
• Bit 11 causes the processor to skip the next instruction if the I/O device is ready.
• Bit 10 clears AC.
• Bit 9 moves a word between AC and the device, initiates another I/O transfer, and clears the device's "ready" flag. These operations take place in a well-defined order that gives useful results if more than one bit is set. More complicated devices, such as disk drives, use these 3 bits in device-specific fashions. Typically, a device decodes the 3 bits to give 8 possible function codes.

OPR (OPERATE)

Many operations are achieved using OPR, including most of the conditionals. OPR does not address a memory location; conditional execution is achieved by conditionally skipping one instruction, which is typically a JMP.

bit of the OPR instruction word specifies a certain action, and the programmer could achieve several actions in a single instruction cycle by setting multiple bits. In use, a programmer can write several instruction mnemonics alongside one another, and the assembler combines them with OR to devise the actual instruction word. Many I/O devices supported IOT instructions. The OPR instructions come in Groups. Bits 3, 8 and 11 identify the Group of an OPR instruction.

Group 1

• 7200 – CLA – Clear Accumulator.
• 7100 – CLL – Clear the L Bit.
• 7040 – CMA – Ones Complement Accumulator.
• 7020 – CML – Complement L Bit.
• 7001 – IAC – Increment.
• 7010 – RAR – Rotate Right.
• 7004 – RAL – Rotate Left.
• 7012 – RTR – Rotate Right Twice.
• 7006 – RTL – Rotate Left Twice.
• 7002 – BSW – Byte Swap 6-bit "bytes" (PDP 8/e and up).

In most cases, the operations are sequenced so that they can be combined in the most useful ways. For example, combining CLA (CLear Accumulator), CLL (CLear Link), and IAC (Increment ACcumulator) first clears the AC and Link, then increments the accumulator, leaving it set to 1. Adding RAL to the mix (so CLA CLL IAC RAL) causes the accumulator to be cleared, incremented, then rotated left, leaving it set to 2. In this way, small integer constants were placed in the accumulator with a single instruction.

The combination CMA IAC, which the assembler lets you abbreviate as CIA, produces the arithmetic inverse of AC: the twos-complement negation. Since there is no subtraction instruction, only the twos-complement add (TAD), computing the difference of two operands, requires first negating the subtrahend.

A Group 1 OPR instruction that has none of bits set performs no action. The programmer can write NOP (No Operation) to assemble such an instruction.

Group 2

• 7600 – CLA – Clear AC.
• 7500 – SMA – Skip on AC (or group).
• 7440 – SZA – Skip on AC .EQ. 0 (or group).
• 7420 – SNL – Skip on L .EQ. 0 (or group).
• 7404 – OSR – logically 'or' front-panel switches with AC.
• 7402 – HLT – Halt.

When bit 8 is clear, a skip is performed if any of the specified conditions are true. For example, "SMA SZA", opcode 7540, skips if AC .LE. 0.

Group 2, AND Group

• 7410 – SKP – Skip Unconditionally.
• 7610 – CLA – Clear AC.
• 7510 – SPA – Skip on AC .GE. 0.
• 7450 – SNA – Skip on AC .NE. 0.
• 7430 – SZL – Skip on L .EQ. 0.

When bit 8 is set, the Group 2, or skip condition is inverted, via De Morgan's laws: the skip is not performed if any of the group 2, Or conditions are true, meaning that all of the specified skip conditions must be true. For example, "SPA SNA", opcode 7550, skips if AC is greater than 0. If none of the bits 5 to 7 are set, then the skip is unconditional.

Group 3

Unused bit combinations of OPR are defined as a third Group of microprogrammed actions mostly affecting the MQ (Multiplier/Quotient) register.

• 7601 – CLA – Clear AC.
• 7501 – MQA – Multiplier Quotient with AC (logical or MQ into AC).
• 7441 – SCA – Step counter load into AC.
• 7421 – MQL – Multiplier Quotient Load (Transfer AC to MQ, clear AC).
• 7621 – CAM – CLA + MQL clears both AC and MQ.

Typically CLA and MQA were combined to transfer MQ into AC. Another useful combination is MQA and MQL, to exchange the two registers.

Three bits specified a multiply/divide instruction to perform:

• 7401 – No operation.
• 7403 – SCL – Step Counter Load (immediate word follows, PDP-8/I and up).
• 7405 – MUY – Multiply.
• 7407 – DVI – Divide.
• 7411 – NMI – Normalize.
• 7413 – SHL – Shift left (immediate word follows).
• 7415 – ASR – Arithmetic shift right.
• 7417 – LSR – Logical shift right.
Sources:
• Adapted from: https://en.wikipedia.org/wiki/PDP-8